An MIS transistor having a projecting gate (also designated as a gate in the form of an inverted T) is known from the publication "Impact of the Gate-Drain Overlapped Device (GOLD) for deep submicrometer VLSI" by R. Izawa, T. Kure and E. Takeda in the magazine I.E.E.E. Transactions on Electron Devices, V. 35, No. 12, December 1988.
A method of manufacturing a transistor of this type intended to constitute integrated circuits having a very high integration density is also indicated in the same publication.
The authors have shown that the limitation of the performances of the MIS transistors of submicron dimensions with respect to the drain breakdown voltage, to the emission of hot carriers and/or to the insufficient transconductance could be obviated by the use of a gate electrode covering the weakly doped parts of the source and drain regions an extending in the direction of the highly doped parts of the regions over a distance which must be optimized.
The gate of the transistors is formed from two distinct layers of polycrystalline silicon so as to obtain the characteristic form of an inverted T. According to the known method, these two polycrystalline layers are separated by an extremely thin oxide layer, of the order of 0.5 to 1 nm thickness, in such a manner that this layer can serve as a reference for the stopping of etching the second polycrystalline layer during the formation of the gate islands, but nevertheless ensures sufficient electrical conduction between the first and the second polycrystalline layer in the interior other widened gate island of the finished device.
A disadvantage inherent in the known method resides in the difficulty to obtain in a reproducible manner an oxide layer having a equally small thickness, which requires a very narrow compromise between the effectiveness of its etch stopper function and a fairly high electrical conduction of this layer so as not to induce parasitic effects in the operation of the transistors and more particularly in the effectiveness of the transmission of the voltages to the lower part of the gates in a wide frequency spectrum.
The invention proposes a modification of the known method in order to avoid the disadvantage mentioned. It is based on the idea that the electrical conduction between the first and the second polycrystalline layer in the interior of the widened gate island of the finished device could be obtained by means independent of the thickness of the so-called first insulating layer and that thus there is a freedom of choice of a more substantial thickness for this layer, which can therefore more readily be obtained in a reproducible and also less critical manner to be used as an etch stopper.